Field Programmable Logic and Application : 14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004. Proceedings

Table of Contents

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   Book Overview
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   Chapter 1 FPGAs and the Era of Field Programmability
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   Chapter 2 Reconfigurable Systems Emerge
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   Chapter 3 System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?
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   Chapter 4 Hardware Accelerated Novel Protein Identification
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   Chapter 5 Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices
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   Chapter 6 A Key Management Architecture for Securing Off-Chip Data Transfers
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   Chapter 7 FPGA Implementation of Biometric Authentication System Based on Hand Geometry
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   Chapter 8 SoftSONIC: A Customisable Modular Platform for Video Applications
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    Chapter 9 Deploying Hardware Platforms for SoC Validation: An Industrial Case Study
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    Chapter 10 Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes
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    Chapter 11 Power Analysis Attacks Against FPGA Implementations of the DES
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    Chapter 12 Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer
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    Chapter 13 Stochastic Simulation for Biochemical Reactions on FPGA
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    Chapter 14 Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures
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    Chapter 15 Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine
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    Chapter 16 Improving FPGA Performance and Area Using an Adaptive Logic Module
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    Chapter 17 A Dual-V DD Low Power FPGA Architecture
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    Chapter 18 Simultaneous Timing Driven Clustering and Placement for FPGAs
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    Chapter 19 Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
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    Chapter 20 Compact Buffered Routing Architecture
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    Chapter 21 On Optimal Irregular Switch Box Designs
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    Chapter 22 Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation
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    Chapter 23 Comparative Study of SRT-Dividers in FPGA
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    Chapter 24 Second Order Function Approximation Using a Single Multiplication on FPGAs
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    Chapter 25 Efficient Modular Division Implementation
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    Chapter 26 A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management
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    Chapter 27 The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures
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    Chapter 28 A High-Density Optically Reconfigurable Gate Array Using Dynamic Method
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    Chapter 29 Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device
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    Chapter 30 Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA
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    Chapter 31 Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays
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    Chapter 32 A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks
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    Chapter 33 Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
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    Chapter 34 BIST Based Interconnect Fault Location for FPGAs
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    Chapter 35 FPGAs BIST Evaluation
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    Chapter 36 Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor
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    Chapter 37 Evaluating Fault Emulation on FPGA
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    Chapter 38 Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs
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    Chapter 39 Multiple Restricted Multiplication
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    Chapter 40 Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices
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    Chapter 41 A Steerable Complex Wavelet Construction and Its Implementation on FPGA
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    Chapter 42 Programmable Logic Has More Computational Power than Fixed Logic
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    Chapter 43 JHDLBits: The Merging of Two Worlds
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    Chapter 44 A System Level Resource Estimation Tool for FPGAs
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    Chapter 45 The PowerPC Backend Molen Compiler
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    Chapter 46 An Integrated Online Scheduling and Placement Methodology
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    Chapter 47 On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities
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    Chapter 48 Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor – An Approach to Tough Cases –
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    Chapter 49 Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters
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    Chapter 50 Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems
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    Chapter 51 Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2
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    Chapter 52 Three-Dimensional Dynamic Programming for Homology Search
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    Chapter 53 An Instance-Specific Hardware Algorithm for Finding a Maximum Clique
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    Chapter 54 IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter
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    Chapter 55 Automatic Creation of Reconfigurable PALs/PLAs for SoC
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    Chapter 56 A Key Agile 17.4 Gbit/sec Camellia Implementation
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    Chapter 57 High Performance True Random Number Generator in Altera Stratix FPLDs
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    Chapter 58 A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays
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    Chapter 59 Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
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    Chapter 60 Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor
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    Chapter 61 Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors
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    Chapter 62 Storage Allocation for Diverse FPGA Memory Specifications
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    Chapter 63 Real Time Optical Flow Processing System
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    Chapter 64 Methods and Tools for High-Resolution Imaging
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    Chapter 65 Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation
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    Chapter 66 A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data
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    Chapter 67 A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems
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    Chapter 68 An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms
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    Chapter 69 HW/SW Co-design by Automatic Embedding of Complex IP Cores
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    Chapter 70 Increasing Pipelined IP Core Utilization in Process Networks Using Exploration
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    Chapter 71 Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs
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    Chapter 72 SOC and RTOS: Managing IPs and Tasks Communications
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    Chapter 73 The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
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    Chapter 74 A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
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    Chapter 75 Power-Driven Design Partitioning
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    Chapter 76 Power Consumption Reduction Through Dynamic Reconfiguration
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    Chapter 77 The XPP Architecture and Its Co-simulation Within the Simulink Environment
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    Chapter 78 An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer
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    Chapter 79 Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration
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    Chapter 80 Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS – High Energy Physics Experiment
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    Chapter 81 Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs
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    Chapter 82 SystemC for the Design and Modeling of Programmable Systems
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    Chapter 83 An Evolvable Hardware Tutorial
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    Chapter 84 A Runtime Environment for Reconfigurable Hardware Operating Systems
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    Chapter 85 A Dynamically Reconfigurable Asynchronous FPGA Architecture
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    Chapter 86 Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures
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    Chapter 87 Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices
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    Chapter 88 Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs
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    Chapter 89 Automating the Layout of Reconfigurable Subsystems via Template Reduction
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    Chapter 90 FPGA Acceleration of Rigid Molecule Interactions
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    Chapter 91 Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path
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    Chapter 92 Exploring Potential Benefits of 3D FPGA Integration
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    Chapter 93 System-Level Modeling of Dynamically Reconfigurable Co-processors
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    Chapter 94 A Development Support System for Applications That Use Dynamically Reconfigurable Hardware
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    Chapter 95 Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures
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    Chapter 96 Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs
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    Chapter 97 Mapping Basic Recursive Structures to Runtime Reconfigurable Hardware
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    Chapter 98 Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA
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     Chapter 99 Java Technology in an FPGA
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     Chapter 100 Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers
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     Chapter 101 The Chess Monster Hydra
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     Chapter 102 FPGA-Efficient Hybrid LUT/CORDIC Architecture
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     Chapter 103 A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays
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     Chapter 104 Design and Implementation of a CFAR Processor for Target Detection
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     Chapter 105 A Parallel FFT Architecture for FPGAs
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     Chapter 106 FPGA Custom DSP for ECG Signal Analysis and Compression
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     Chapter 107 FPGA Implementation of Adaptive Multiuser Detector for DS-CDMA Systems
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     Chapter 108 Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design
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     Chapter 109 A Low Power FPAA for Wide Band Applications
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     Chapter 110 Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
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     Chapter 111 Real-Time Computation of the Generalized Hough Transform
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     Chapter 112 Minimum Sum of Absolute Differences Implementation in a Single FPGA Device
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     Chapter 113 Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic
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     Chapter 114 High Throughput Serpent Encryption Implementation
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     Chapter 115 Implementation of Elliptic Curve Cryptosystems over GF(2 $^{\mbox{\small n}}$ ) in Optimal Normal Basis on a Reconfigurable Computer
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     Chapter 116 Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V
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     Chapter 117 A Reconfigurable Communication Processor Compatible with Different Industrial Fieldbuses
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     Chapter 118 Multithreading in a Hyper-programmable Platform for Networked Systems
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     Chapter 119 An Environment for Exploring Data-Driven Architectures
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     Chapter 120 FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T
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     Chapter 121 A Dynamic NoC Approach for Communication in Reconfigurable Devices
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     Chapter 122 Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems
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     Chapter 123 FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications
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     Chapter 124 A Structured Methodology for System-on-an-FPGA Design
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     Chapter 125 Secure Logic Synthesis
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     Chapter 126 Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion
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     Chapter 127 The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead
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     Chapter 128 Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory
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     Chapter 129 FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat Head
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     Chapter 130 FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation
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     Chapter 131 Processing Repetitive Sequence Structures with Mismatches at Streaming Rate
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     Chapter 132 Artificial Neural Networks Processor – A Hardware Implementation Using a FPGA
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     Chapter 133 FPGA Implementation of the Ridge Line Following Fingerprint Algorithm
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     Chapter 134 A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals
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     Chapter 135 Flow Monitoring in High-Speed Networks with 2D Hash Tables
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     Chapter 136 A VHDL Generator for Elliptic Curve Cryptography
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     Chapter 137 FPGA-Based Parallel Comparison of Run-Length-Encoded Strings
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     Chapter 138 Real Environments Image Labelling Based on Reconfigurable Architectures
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     Chapter 139 Object Oriented Programming Paradigms for the VHDL
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     Chapter 140 Using Reconfigurable Hardware Through Web Services in Distributed Applications
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     Chapter 141 Data Reuse in Configurable Architectures with RAM Blocks
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     Chapter 142 A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development
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     Chapter 143 AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits
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     Chapter 144 A Self-Reconfiguration Framework for Multiprocessor CSoPCs
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     Chapter 145 A Virtual File System for Dynamically Reconfigurable FPGAs
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     Chapter 146 Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array
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     Chapter 147 Design and Implementation of the Memory Scheduler for the PC-Based Router
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     Chapter 148 Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach
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     Chapter 149 Intellectual Property Protection for RNS Circuits on FPGAs
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     Chapter 150 FPGA Implementation of a Tool Breakage Detection Algorithm in CNC Milling Machines
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     Chapter 151 Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector
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     Chapter 152 Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA
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     Chapter 153 FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot
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     Chapter 154 Real-Time Detection of Moving Objects
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     Chapter 155 Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAs
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     Chapter 156 Versatile Imaging Architecture Based on a System on Chip
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     Chapter 157 A Hardware Implementation of a Content Based Image Retrieval Algorithm
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     Chapter 158 Optimization Algorithms for Dynamic Reconfigurable Embedded Systems
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     Chapter 159 Low Power Reconfigurable Devices
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     Chapter 160 Code Re-ordering for a Class of Reconfigurable Microprocessors
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     Chapter 161 Design Space Exploration for Distributed Hardware Reconfigurable Systems
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     Chapter 162 TPR: Three-D Place and Route for FPGAs
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     Chapter 163 Implementing Graphics Shaders Using FPGAs
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     Chapter 164 Preemptive Hardware Task Management
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     Chapter 165 Automated Speculation and Parallelism in High Performance Network Applications
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     Chapter 166 Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems
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     Chapter 167 A Specific Scheduling Flow for Dynamically Reconfigurable Hardware
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     Chapter 168 Design and Evaluation of an FPGA Architecture for Software Protection
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     Chapter 169 Scalable Defect Tolerance Beyond the SIA Roadmap
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     Chapter 170 Run-Time Reconfiguration Management for Adaptive High-Performance Computing Systems
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     Chapter 171 Optimized Field Programmable Gate Array Based Function Evaluation
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     Chapter 172 MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks
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     Chapter 173 A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware
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     Chapter 174 On Computing Maximum Likelihood Phylogeny Using FPGA
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     Chapter 175 Minimising Reconfiguration Overheads in Embedded Applications (Abstract)
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     Chapter 176 Application Specific Small-Scale Reconfigurability
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     Chapter 177 Efficient FPGA-Based Security Kernels