A closed-loop ASIC design approach based on logical effort theory and artificial neural networks
Article in Integration (November 2019)
Closing the Gap Between ASIC
Overview of attention for book
Table of Contents
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Altmetric BadgeBook Overview
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Altmetric BadgeChapter 1 Introduction and Overview of the Book
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Altmetric BadgeChapter 2 Improving Performance through Microarchitecture
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Altmetric BadgeChapter 3 Reducing the Timing Overhead
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Altmetric BadgeChapter 4 High-Speed Logic, Circuits, Libraries and Layout
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Altmetric BadgeChapter 5 Finding Peak Performance in a Process
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Altmetric BadgeChapter 6 Physical Prototyping Plans for High Performance
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Altmetric BadgeChapter 7 Automatic Replacement of Flip-Flops by Latches in ASICs
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Altmetric BadgeChapter 8 Useful-Skew Clock Synthesis Boosts ASIC Performance
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Altmetric BadgeChapter 9 Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing
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Altmetric BadgeChapter 10 Design Optimization with Automated Flex-Cell Creation
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Altmetric BadgeChapter 11 Exploiting Structure and Managing Wires to Increase Density and Performance
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Altmetric BadgeChapter 12 Semi-Custom Methods in a High-Performance Microprocessor Design
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Altmetric BadgeChapter 13 Controlling Uncertainty in High Frequency Designs
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Altmetric BadgeChapter 14 Increasing Circuit Performance through Statistical Design Techniques
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Altmetric BadgeChapter 15 Achieving 550MHz in a Standard Cell ASIC Methodology
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Altmetric BadgeChapter 16 The iCORE™ 520MHz Synthesizable CPU Core
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Altmetric BadgeChapter 17 Creating Synthesizable ARM Processors with Near Custom Performance
Attention for Chapter 9:
Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing
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Citations
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