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Hardware Design and Petri Nets

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Cover of 'Hardware Design and Petri Nets'

Table of Contents

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    Book Overview
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    Chapter 1 Comprehensive Causal Specification of Asynchronous Controller and Arbiter Behaviour
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    Chapter 2 Complementing Role Models with Petri Nets in Studying Asynchronous Data Communications
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    Chapter 3 Petri Net Representations of Computational and Communication Operators
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    Chapter 4 Properties of Change Diagrams
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    Chapter 5 LTrL-Based Model Checking for a Restricted Class of Signal Transition Graphs
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    Chapter 6 A Polynomial Algorithm to Compute the Concurrency Relation of a Regular STG
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    Chapter 7 Synthesis of Synchronous Digital Systems Specified by Petri Nets
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    Chapter 8 Deriving Signal Transition Graphs from Behavioral Verilog HDL
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    Chapter 9 The Design of the Control Circuits for an Asynchronous Instruction Prefetch Unit Using Signal Transition Graphs
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    Chapter 10 Electronic System Design Automation Using High Level Petri Nets
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    Chapter 11 An Evolutionary Approach to the Use of Petri Net Based Models
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    Chapter 12 Modelling and Implementation of Petri Nets Using VHDL
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    Chapter 13 Performance Analysis of Asynchronous Circuits and Systems Using Stochastic Timed Petri Nets
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    Chapter 14 Performance Analysis of Dataflow Architectures Using Timed Coloured Petri Nets
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    Chapter 15 Modeling a Memory Subsystem with Petri Nets: A Case Study
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    Chapter 16 Performance Modeling of Multithreaded Distributed Memory Architectures
Attention for Chapter 12: Modelling and Implementation of Petri Nets Using VHDL
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Chapter title
Modelling and Implementation of Petri Nets Using VHDL
Chapter number 12
Book title
Hardware Design and Petri Nets
Published by
Springer, Boston, MA, January 2000
DOI 10.1007/978-1-4757-3143-9_12
Book ISBNs
978-1-4419-4969-1, 978-1-4757-3143-9
Authors

Dave Prothero, Prothero, Dave