Computer Aided Verification

Table of Contents

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   Book Overview
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   Chapter 1 Logic synthesis and design verification
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   Chapter 2 Efficient verification with BDDs using implicitly conjoined invariants
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   Chapter 3 Parametric circuit representation using inductive Boolean functions
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   Chapter 4 An iterative approach to language containment
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   Chapter 5 BDD-Based debugging of designs using language containment and fair CTL
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   Chapter 6 Reliable hashing without collision detection
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   Chapter 7 A tool for symbolic program verification and abstraction
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   Chapter 8 Symbolic equivalence checking
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    Chapter 9 A decision algorithm for full propositional temporal logic
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    Chapter 10 Reachability and recurrence in Extended Finite State Machines: Modular Vector Addition Systems
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    Chapter 11 Automatic generation of network invariants for the verification of iterative sequential systems
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    Chapter 12 A Graphical Interval Logic toolset for verifying concurrent systems
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    Chapter 13 Combining model checking and theorem proving to verify parallel processes
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    Chapter 14 Verification of a multiplier: 64 bits and beyond
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    Chapter 15 Protocol design for an automated highway system
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    Chapter 16 Computing accumulated delays in real-time systems
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    Chapter 17 Reachability analysis of planar multi-linear systems
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    Chapter 18 An efficient algorithm for minimizing real-time transition systems
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    Chapter 19 Verification of timing properties of VHDL
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    Chapter 20 Alternating RQ timed automata
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    Chapter 21 Timed modal specification — Theory and tools
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    Chapter 22 A mechanically verified application for a mechanically verified environment
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    Chapter 23 Verification of real-time systems using PVS
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    Chapter 24 The formal verification of an algorithm for interactive consistency under a hybrid fault model
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    Chapter 25 Computer-assisted simulation proofs
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    Chapter 26 A verifier and timing analyser for simple imperative programs
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    Chapter 27 Efficient verification of parallel real-time systems
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    Chapter 28 Delay analysis in synchronous programs
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    Chapter 29 Verifying quantitative real-time properties of synchronous programs
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    Chapter 30 A modal logic for message passing processes
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    Chapter 31 Functionality decomposition by compositional correctness preserving transformation
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    Chapter 32 On model-checking for fragments of μ-calculus
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    Chapter 33 On-the-fly verification with stubborn sets
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    Chapter 34 All from one, one for all: on model checking using representatives
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    Chapter 35 Verifying timed behavior automata with input/output critical races
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    Chapter 36 Refining dependencies improves partial-order verification methods (extended abstract)
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    Chapter 37 Exploiting symmetry in temporal logic model checking
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    Chapter 38 Symmetry and model checking
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    Chapter 39 Generation of reduced models for checking fragments of CTL
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    Chapter 40 A Structural linearization principle for processes