↓ Skip to main content
What is this page? Embed badge

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

Overview of attention for book
Cover of 'Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Embedded Memories: Introduction
  3. Altmetric Badge
    Chapter 2 Gain-Cell eDRAMs (GC-eDRAMs): Review of Basics and Prior Art
  4. Altmetric Badge
    Chapter 3 Retention Time Modeling: The Key to Low-Power GC-eDRAMs
  5. Altmetric Badge
    Chapter 4 Conventional GC-eDRAMs Scaled to Near-Threshold Voltage (NTV)
  6. Altmetric Badge
    Chapter 5 Novel Bitcells and Assist Techniques for NTV GC-eDRAMs
  7. Altmetric Badge
    Chapter 6 Aggressive Technology and Voltage Scaling (Down to the Subthreshold Domain)
  8. Altmetric Badge
    Chapter 7 Novel Bitcells for Scaled CMOS Nodes and Soft Error Tolerance
  9. Altmetric Badge
    Chapter 8 Conclusions
Attention for Chapter 5: Novel Bitcells and Assist Techniques for NTV GC-eDRAMs
Altmetric Badge

Citations

dimensions_citation
21 Dimensions
Summary Dimensions citations
So far, Dimensions has found 21 publications that cite this research output.

21

The most recent citing publications are shown below. View all 21 publications that cite this research output on Dimensions.

This page shows the most recent citations of this research output.

Click here to find out how to access more activity.

This page is provided by Altmetric.