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| Chapter title |
Logic Level Modeling
|
|---|---|
| Chapter number | 6 |
| Book title |
The Verilog® Hardware Description Language
|
| Published by |
Springer, Boston, MA, January 2008
|
| DOI | 10.1007/978-0-387-85344-4_6 |
| Book ISBNs |
978-0-387-84930-0, 978-0-387-85344-4
|