Power-Aware Computer Systems

Chapter 1 Early-Stage Definition of LPX: A Low Power Issue-Execute Processor

Chapter 2 Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints

Chapter 3 A Hardware Architecture for Dynamic Performance and Energy Adaptation

Chapter 4 Multi-Processor Computer System Having Low Power Consumption

Chapter 5 An Integrated Heuristic Approach to Power-Aware Real-Time Scheduling

Chapter 6 Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources

Chapter 7 A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics

Chapter 8 Energy-Driven Statistical Sampling: Detecting Software Hotspots

Chapter 9 Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets

Chapter 10 SimDVS: An Integrated Simulation Environment for Performance Evaluation of Dynamic Voltage Scaling Algorithms

Chapter 12 Energy-Efficient Server Clusters

Chapter 13 Single Region vs. Multiple Regions: A Comparison of Different Compiler-Directed Dynamic Voltage Scheduling Approaches