VLSI Systems and Computations

Table of Contents

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   Book Overview
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   Chapter 1 The Optical Mouse, and an Architectural Methodology for Smart Digital Sensors
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   Chapter 2 Designing VLSI Processor-Aids and Architectures
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   Chapter 3 Keys to Successful VLSI System Design
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   Chapter 4 Programmable LSI Digital Signal Processor Development
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   Chapter 5 Functional Parallelism in VLSI Systems and Computations
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   Chapter 6 Functional Extensibility: Making the World Safe for VLSI
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   Chapter 7 Replication of Inputs May Save Computational Resources in VLSI
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   Chapter 8 Planar Circuit Complexity and The Performance of VLSI Algorithms +
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    Chapter 9 Three-Dimensional Integrated Circuitry
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    Chapter 10 A Critique and an Appraisal of VLSI Models of Computation
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    Chapter 11 On the Complexity of VLSI Computations
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    Chapter 12 On the Area Required by VLSI Circuits
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    Chapter 13 The VLSI Complexity of Sorting
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    Chapter 14 Minimum Edge Length Planar Embeddings of Trees
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    Chapter 15 The VLSI Approach to Computational Complexity
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    Chapter 16 Optimal Placement for River Routing
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    Chapter 17 The Separation for General Single-Layer Wiring Barriers
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    Chapter 18 Provably Good Channel Routing Algorithms
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    Chapter 19 Optimal Routing in Rectilinear Channels
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    Chapter 20 New Lower Bounds for Channel Width
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    Chapter 21 Compact Layouts of Banyan/FFT Networks
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    Chapter 22 Syntax-Directed Verification of Circuit Function
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    Chapter 23 Temporal Specifications of Self-Timed Systems
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    Chapter 24 A Mathematical Approach to Modelling the Flow of Data and Control in Computational Networks
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    Chapter 25 A Wavefront Notation Tool for VLSI Array Design
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    Chapter 26 A Matrix Data Flow Language/Architecture for Parallel Matrix Operations Based on Computational Wavefront Concept
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    Chapter 27 Digital Signal Processing Applications of Systolic Algorithms
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    Chapter 28 A Two-Level Pipelined Systolic Array for Convolutions
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    Chapter 29 Systolic Algorithms for Running Order Statistics in Signal and Image Processing
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    Chapter 30 Systolic Array Processor Developments
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    Chapter 31 A Systolic (VLSI) Array for Processing Simple Relational Queries
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    Chapter 32 A Systolic Data Structure Chip for Connectivity Problems
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    Chapter 33 Fixed-Point High-Speed Parallel Multipliers in VLSI
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    Chapter 34 A Mesh-Connected Area-Time Optimal VLSI Integer Multiplier
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    Chapter 35 A Regular Layout for Parallel Multiplier of 0(Log 2 N) Time
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    Chapter 36 VLSI Implementations of a Reduced Instruction Set Computer
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    Chapter 37 MIPS: A VLSI Processor Architecture
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    Chapter 38 Comparative Survey of Different Design Methodologies for Control Part of Microprocessors
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    Chapter 39 C.fast: A Fault Tolerant and Self Testing Microprocessor
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    Chapter 40 VLSI Processor Arrays for Matrix Manipulation
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    Chapter 41 A General-Purpose Cam-Based System
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    Chapter 42 A Statically Scheduled VLSI Interconnect for Parallel Processors
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    Chapter 43 The CMOS SLA Implementation and SLA Program Structures
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    Chapter 44 A New CCD Parallel Processing Architecture