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Network-on-Chip Architectures

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Cover of 'Network-on-Chip Architectures'

Table of Contents

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    Book Overview
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    Chapter 1 Introduction
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    Chapter 2 A Baseline NoC Architecture
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    Chapter 3 ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]
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    Chapter 4 RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]
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    Chapter 5 Exploring FaultoTolerant Network-on-Chip Architectures [37]
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    Chapter 6 On the Effects of Process Variation in Network-on-Chip Architectures [45]
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    Chapter 7 The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]
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    Chapter 8 Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]
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    Chapter 9 A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]
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    Chapter 10 Digest of Additional NoC MACRO-Architectural Research
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    Chapter 11 Conclusions and Future Work
Attention for Chapter 4: RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]
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