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The g m / I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits

Overview of attention for book
Attention for Chapter 1: Sizing the Intrinsic Gain Stage
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Chapter title
Sizing the Intrinsic Gain Stage
Chapter number 1
Book title
The g m / I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits
Published by
Springer, Boston, MA, January 2010
DOI 10.1007/978-0-387-47101-3_1
Book ISBNs
978-0-387-47100-6, 978-0-387-47101-3
Authors

Paul G. A. Jespers, Jespers, Paul G. A.

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 6 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 6 100%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 2 33%
Student > Master 2 33%
Other 1 17%
Researcher 1 17%
Readers by discipline Count As %
Engineering 5 83%
Arts and Humanities 1 17%