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Chapter title |
Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop
|
---|---|
Chapter number | 20 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2009
|
DOI | 10.1007/978-3-642-11802-9_20 |
Book ISBNs |
978-3-64-211801-2, 978-3-64-211802-9
|
Authors |
Hossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi |