High Performance Embedded Architectures and Compilers

Table of Contents

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   Book Overview
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   Chapter 1 Keynote: Challenges on the Road to Exascale Computing
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   Chapter 2 Keynote: Compilers in the Manycore Era
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   Chapter 3 High Performance Embedded Architectures and Compilers
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   Chapter 4 Predictive Runtime Code Scheduling for Heterogeneous Architectures
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   Chapter 5 Collective Optimization
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   Chapter 6 High Speed CPU Simulation Using LTU Dynamic Binary Translation
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   Chapter 7 Integrated Modulo Scheduling for Clustered VLIW Architectures
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   Chapter 8 Software Pipelining in Nested Loops with Prolog-Epilog Merging
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    Chapter 9 A Flexible Code Compression Scheme Using Partitioned Look-Up Tables
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    Chapter 10 MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor
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    Chapter 11 IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor
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    Chapter 12 A Hardware Task Scheduler for Embedded Video Processing
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    Chapter 13 Finding Stress Patterns in Microprocessor Workloads
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    Chapter 14 Deriving Efficient Data Movement from Decoupled Access/Execute Specifications
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    Chapter 15 MPSoC Design Using Application-Specific Architecturally Visible Communication
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    Chapter 16 Communication Based Proactive Link Power Management
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    Chapter 17 Mapping and Synchronizing Streaming Applications on Cell Processors
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    Chapter 18 Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
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    Chapter 19 Accomodating Diversity in CMPs with Heterogeneous Frequencies
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    Chapter 20 A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip
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    Chapter 21 Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
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    Chapter 22 Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines
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    Chapter 23 HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
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    Chapter 24 Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures
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    Chapter 25 Revisiting Cache Block Superloading
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    Chapter 26 ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
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    Chapter 27 In-Network Caching for Chip Multiprocessors
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    Chapter 28 Parallel LDPC Decoding on the Cell/B.E. Processor
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    Chapter 29 Parallel H.264 Decoding on an Embedded Multicore Processor