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Emerging Memory Technologies

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Cover of 'Emerging Memory Technologies'

Table of Contents

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    Book Overview
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    Chapter 1 Introduction
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    Chapter 2 NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-volatile Memory
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    Chapter 3 A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement
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    Chapter 4 Energy Efficient Systems Using Resistive Memory Devices
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    Chapter 5 Asymmetry in STT-RAM Cell Operations
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    Chapter 6 An Energy-Efficient 3D Stacked STT-RAM Cache Architecture for CMPs
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    Chapter 7 STT-RAM Cache Hierarchy Design and Exploration with Emerging Magnetic Devices
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    Chapter 8 Resistive Memories in Associative Computing
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    Chapter 9 Wear-Leveling Techniques for Nonvolatile Memories
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    Chapter 10 A Circuit-Architecture Co-optimization Framework for Exploring Nonvolatile Memory Hierarchies
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    Chapter 11 Ferroelectric Nonvolatile Processor Design, Optimization, and Application
Attention for Chapter 5: Asymmetry in STT-RAM Cell Operations
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Chapter title
Asymmetry in STT-RAM Cell Operations
Chapter number 5
Book title
Emerging Memory Technologies
Published by
Springer, New York, NY, January 2014
DOI 10.1007/978-1-4419-9551-3_5
Book ISBNs
978-1-4419-9550-6, 978-1-4419-9551-3
Authors

Yaojun Zhang, Wujie Wen, Yiran Chen, Zhang, Yaojun, Wen, Wujie, Chen, Yiran

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