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Validation of Railway Interlocking Systems by Formal Verification, A Case Study. - Andrea Bonacchi 0001, Alessandro… http://t.co/WlYoeFs8sp
Validation of Railway Interlocking Systems by Formal Verification, A Case Study. - Andrea Bonacchi 0001, Alessandro… http://t.co/WlYoeFs8sp
Compliance and Testing Preorders Differ. - Giovanni Bernardi 0001, Matthew Hennessy http://t.co/k5Y4utiIHE
Towards Proving RISC Machine Code not Risky with respect to Memory Aliasing. (arXiv:1305.6431v1 [cs.LO]) http://t.co/oqVYkwIdDC