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High Performance Embedded Architectures and Compilers

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Cover of 'High Performance Embedded Architectures and Compilers'

Table of Contents

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    Book Overview
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    Chapter 1 Embedded Systems as Datacenters
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    Chapter 2 Larrabee: A Many-Core Intel Architecture for Visual Computing
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    Chapter 3 Remote Store Programming
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    Chapter 4 Low-Overhead, High-Speed Multi-core Barrier Synchronization
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    Chapter 5 High Performance Embedded Architectures and Compilers
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    Chapter 6 Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems
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    Chapter 7 Split Register Allocation: Linear Complexity Without the Performance Penalty
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    Chapter 8 Trace-Based Data Layout Optimizations for Multi-core Processors
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    Chapter 9 Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors
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    Chapter 10 Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures
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    Chapter 11 Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
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    Chapter 12 Accelerating XML Query Matching through Custom Stack Generation on FPGAs
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    Chapter 13 An Application-Aware Load Balancing Strategy for Network Processors
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    Chapter 14 Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays
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    Chapter 15 Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors
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    Chapter 16 Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors
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    Chapter 17 RELOCATE: Re gister File Loc al A ccess Pat te rn Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor
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    Chapter 18 Performance and Power Aware CMP Thread Allocation Modeling
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    Chapter 19 Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching
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    Chapter 20 Scalable Shared-Cache Management by Containing Thrashing Workloads
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    Chapter 21 SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs
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    Chapter 22 DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems
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    Chapter 23 Tagged Procedure Calls ( TPC ): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor
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    Chapter 24 Analysis of Task Offloading for Accelerators
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    Chapter 25 Offload – Automating Code Migration to Heterogeneous Multicore Systems
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    Chapter 26 Computer Generation of Efficient Software Viterbi Decoders
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Title
High Performance Embedded Architectures and Compilers
Published by
Springer Science & Business Media, January 2010
DOI 10.1007/978-3-642-11515-8
ISBNs
978-3-64-211514-1, 978-3-64-211515-8
Editors

Patt, Yale N., Foglia, Pierfrancesco, Duesterwald, Evelyn, Faraboschi, Paolo, Martorell, Xavier

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X Demographics

The data shown below were collected from the profile of 1 X user who shared this research output. Click here to find out more about how the information was compiled.
Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 22 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Germany 1 5%
Taiwan 1 5%
Finland 1 5%
United States 1 5%
Belgium 1 5%
Unknown 17 77%

Demographic breakdown

Readers by professional status Count As %
Student > Master 6 27%
Student > Ph. D. Student 6 27%
Researcher 3 14%
Student > Bachelor 3 14%
Professor 1 5%
Other 2 9%
Unknown 1 5%
Readers by discipline Count As %
Computer Science 14 64%
Engineering 4 18%
Psychology 2 9%
Physics and Astronomy 1 5%
Unknown 1 5%