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Reconfigurable Computing: Architectures and Applications

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Cover of 'Reconfigurable Computing: Architectures and Applications'

Table of Contents

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    Book Overview
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    Chapter 1 Implementation of Realtime and Highspeed Phase Detector on FPGA
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    Chapter 2 Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform
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    Chapter 3 Configurable Embedded Core for Controlling Electro-Mechanical Systems
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    Chapter 4 Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors
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    Chapter 5 Dynamic Partial Reconfigurable FIR Filter Design
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    Chapter 6 Event-Driven Simulation Engine for Spiking Neural Networks on a Chip
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    Chapter 7 Towards an Optimal Implementation of MLP in FPGA
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    Chapter 8 Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture
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    Chapter 9 Quality Driven Dynamic Low Power Reconfiguration of Handhelds
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    Chapter 10 An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects
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    Chapter 11 Highly Paralellized Architecture for Image Motion Estimation
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    Chapter 12 Design Exploration of a Video Pre-processor for an FPGA Based SoC
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    Chapter 13 QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection
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    Chapter 14 Applications of Small-Scale Reconfigurability to Graphics Processors
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    Chapter 15 An Embedded Multi-camera System for Simultaneous Localization and Mapping
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    Chapter 16 Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor
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    Chapter 17 Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip
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    Chapter 18 Handel-C Design Enhancement for FPGA-Based DV Decoder
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    Chapter 19 Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform
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    Chapter 20 A New VLSI Architecture of Lifting-Based DWT
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    Chapter 21 Architecture Based on FPGA’s for Real-Time Image Processing
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    Chapter 22 Real Time Image Processing on a Portable Aid Device for Low Vision Patients
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    Chapter 23 General Purpose Real-Time Image Segmentation System
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    Chapter 24 Implementation of LPM Address Generators on FPGAs
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    Chapter 25 Self Reconfiguring EPIC Soft Core Processors
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    Chapter 26 Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs
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    Chapter 27 Area/Performance Improvement of NoC Architectures
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    Chapter 28 Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array
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    Chapter 29 A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
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    Chapter 30 Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support
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    Chapter 31 A Reconfigurable Data Cache for Adaptive Processors
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    Chapter 32 The Emergence of Non-von Neumann Processors
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    Chapter 33 Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server
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    Chapter 34 A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs
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    Chapter 35 A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI
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    Chapter 36 PISC: Polymorphic Instruction Set Computers
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    Chapter 37 Generic Network Interfaces for Plug and Play NoC Based Architecture
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    Chapter 38 Providing QoS Guarantees in a NoC by Virtual Channel Reservation
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    Chapter 39 Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA
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    Chapter 40 A Reconfigurable Architecture for MIMO Square Root Decoder
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    Chapter 41 Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking
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    Chapter 42 Updates on the Security of FPGAs Against Power Analysis Attacks
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    Chapter 43 Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems
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    Chapter 44 FPGA Implementation of a GF (2 m ) Tate Pairing Architecture
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    Chapter 45 Iterative Modular Division over GF(2 m ): Novel Algorithm and Implementations on FPGA
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    Chapter 46 Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider
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    Chapter 47 UNITE: Uniform Hardware-Based Network Intrusion deTection Engine
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    Chapter 48 Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs
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    Chapter 49 Automatic Compilation Framework for Bloom Filter Based Intrusion Detection
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    Chapter 50 A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware
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    Chapter 51 Reconfigurable Computing: Architectures and Applications
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    Chapter 52 Integrating Custom Instruction Specifications into C Development Processes
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    Chapter 53 A Compiler-Oriented Architecture Description for Reconfigurable Systems
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    Chapter 54 Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility
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    Chapter 55 High-Level Synthesis Using SPARK and Systolic Array
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    Chapter 56 Super Semi-systolic Array-Based Application-Specific PLD Architecture
Overall attention for this book and its chapters
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Mentioned by

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2 Wikipedia pages

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16 Mendeley
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Title
Reconfigurable Computing: Architectures and Applications
Published by
Springer Science & Business Media, July 2006
DOI 10.1007/11802839
ISBNs
978-3-54-036708-6, 978-3-54-036863-2
Editors

Bertels, Koen, Cardoso, João M. P., Vassiliadis, Stamatis

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Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 16 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Portugal 1 6%
Germany 1 6%
Unknown 14 88%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 6 38%
Student > Doctoral Student 2 13%
Student > Master 2 13%
Student > Postgraduate 2 13%
Professor 1 6%
Other 3 19%
Readers by discipline Count As %
Computer Science 7 44%
Engineering 6 38%
Agricultural and Biological Sciences 1 6%
Neuroscience 1 6%
Social Sciences 1 6%
Other 0 0%

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