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Timeline
Chapter title |
An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors
|
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Chapter number | 62 |
Book title |
Advances in Computer Systems Architecture
|
Published by |
Springer, Berlin, Heidelberg, September 2006
|
DOI | 10.1007/11859802_62 |
Book ISBNs |
978-3-54-040056-1, 978-3-54-040058-5
|
Authors |
Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing |