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| Chapter title |
Randomization, Coverage and Assertion Gotchas
|
|---|---|
| Chapter number | 7 |
| Book title |
Verilog and SystemVerilog Gotchas
|
| Published by |
Springer, Boston, MA, January 2007
|
| DOI | 10.1007/978-0-387-71715-9_7 |
| Book ISBNs |
978-0-387-71714-2, 978-0-387-71715-9
|
| Authors |
Stuart Sutherland, Don Mills |