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Power Aware Design Methodologies

Overview of attention for book
Cover of 'Power Aware Design Methodologies'

Table of Contents

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    Book Overview
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    Chapter 1 Introduction
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    Chapter 2 CMOS Device Technology Trends for Power-Constrained Applications
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    Chapter 3 Low Power Memory Design
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    Chapter 4 Low-Power Digital Circuit Design
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    Chapter 5 Low Voltage Analog Design
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    Chapter 6 Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip
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    Chapter 7 Power Optimization by Datapath Width Adjustment
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    Chapter 8 Energy-Efficient Design of High-Speed Links
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    Chapter 9 System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing
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    Chapter 10 Tools and Techniques for Integrated Hardware-Software Energy Optimizations
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    Chapter 11 Power-Aware Communication Systems
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    Chapter 12 Power-Aware Wireless Microsensor Networks
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    Chapter 13 Circuit and System Level Power Management
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    Chapter 14 Tools and Methodologies for Power Sensitive Design
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    Chapter 15 Reconfigurable Processors — The Road to Flexible Power-Aware Computing
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    Chapter 16 Energy-Efficient System-Level Design
Attention for Chapter 6: Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip
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Chapter title
Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip
Chapter number 6
Book title
Power Aware Design Methodologies
Published by
Springer, Boston, MA, January 2002
DOI 10.1007/0-306-48139-1_6
Book ISBNs
978-1-4020-7152-2, 978-0-306-48139-0
Authors

Chulwoo Kim, Sung-Mo Steve Kang, Kim, Chulwoo, Kang, Sung-Mo Steve

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