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High Performance Embedded Architectures and Compilers

Overview of attention for book
Cover of 'High Performance Embedded Architectures and Compilers'

Table of Contents

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    Book Overview
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    Chapter 1 Embedded Systems as Datacenters
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    Chapter 2 Larrabee: A Many-Core Intel Architecture for Visual Computing
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    Chapter 3 Remote Store Programming
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    Chapter 4 Low-Overhead, High-Speed Multi-core Barrier Synchronization
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    Chapter 5 High Performance Embedded Architectures and Compilers
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    Chapter 6 Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems
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    Chapter 7 Split Register Allocation: Linear Complexity Without the Performance Penalty
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    Chapter 8 Trace-Based Data Layout Optimizations for Multi-core Processors
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    Chapter 9 Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors
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    Chapter 10 Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures
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    Chapter 11 Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
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    Chapter 12 Accelerating XML Query Matching through Custom Stack Generation on FPGAs
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    Chapter 13 An Application-Aware Load Balancing Strategy for Network Processors
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    Chapter 14 Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays
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    Chapter 15 Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors
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    Chapter 16 Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors
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    Chapter 17 RELOCATE: Re gister File Loc al A ccess Pat te rn Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor
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    Chapter 18 Performance and Power Aware CMP Thread Allocation Modeling
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    Chapter 19 Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching
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    Chapter 20 Scalable Shared-Cache Management by Containing Thrashing Workloads
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    Chapter 21 SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs
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    Chapter 22 DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems
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    Chapter 23 Tagged Procedure Calls ( TPC ): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor
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    Chapter 24 Analysis of Task Offloading for Accelerators
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    Chapter 25 Offload – Automating Code Migration to Heterogeneous Multicore Systems
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    Chapter 26 Computer Generation of Efficient Software Viterbi Decoders
Attention for Chapter 7: Split Register Allocation: Linear Complexity Without the Performance Penalty
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About this Attention Score

  • Good Attention Score compared to outputs of the same age (72nd percentile)
  • High Attention Score compared to outputs of the same age and source (80th percentile)

Mentioned by

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1 X user
wikipedia
1 Wikipedia page

Citations

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5 Dimensions

Readers on

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6 Mendeley
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Chapter title
Split Register Allocation: Linear Complexity Without the Performance Penalty
Chapter number 7
Book title
High Performance Embedded Architectures and Compilers
Published in
Lecture notes in computer science, January 2010
DOI 10.1007/978-3-642-11515-8_7
Book ISBNs
978-3-64-211514-1, 978-3-64-211515-8
Authors

Boubacar Diouf, Albert Cohen, Fabrice Rastello, John Cavazos, Diouf, Boubacar, Cohen, Albert, Rastello, Fabrice, Cavazos, John

X Demographics

X Demographics

The data shown below were collected from the profile of 1 X user who shared this research output. Click here to find out more about how the information was compiled.
Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 6 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
China 1 17%
Unknown 5 83%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 3 50%
Student > Master 2 33%
Other 1 17%
Readers by discipline Count As %
Computer Science 6 100%
Attention Score in Context

Attention Score in Context

This research output has an Altmetric Attention Score of 4. This is our high-level measure of the quality and quantity of online attention that it has received. This Attention Score, as well as the ranking and number of research outputs shown below, was calculated when the research output was last mentioned on 17 January 2019.
All research outputs
#7,225,360
of 25,046,311 outputs
Outputs from Lecture notes in computer science
#2,162
of 8,152 outputs
Outputs of similar age
#44,292
of 174,869 outputs
Outputs of similar age from Lecture notes in computer science
#35
of 184 outputs
Altmetric has tracked 25,046,311 research outputs across all sources so far. This one has received more attention than most of these and is in the 69th percentile.
So far Altmetric has tracked 8,152 research outputs from this source. They typically receive a little more attention than average, with a mean Attention Score of 5.2. This one has gotten more attention than average, scoring higher than 72% of its peers.
Older research outputs will score higher simply because they've had more time to accumulate mentions. To account for age we can compare this Altmetric Attention Score to the 174,869 tracked outputs that were published within six weeks on either side of this one in any source. This one has gotten more attention than average, scoring higher than 72% of its contemporaries.
We're also able to compare this research output to 184 others from the same source and published within six weeks on either side of this one. This one has done well, scoring higher than 80% of its contemporaries.