Chapter 1 FPGA-Based High-Speed Authenticated Encryption System

Chapter 2 A Smart Memory Accelerated Computed Tomography Parallel Backprojection

Chapter 3 Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure

Chapter 5 An Ultra-Low-Power Application-Specific Processor with Sub-V T Memories for Compressed Sensing

Chapter 6 Configurable Low-Latency Interconnect for Multi-core Clusters

Chapter 7 A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Chapter 8 Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections

Chapter 9 On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

Chapter 10 SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

Chapter 11 CMOS Implementation of Threshold Gates with Hysteresis

Chapter 12 Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates