VLSI for Artificial Intelligence

Table of Contents

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   Book Overview
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   Chapter 1 From Low Level Semantic Description of Prolog to Instruction Set and VLSI Design
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   Chapter 2 A 32 Bit Processor for Compiled Prolog
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   Chapter 3 Carmel-1: A VLSI Architecture for Flat Concurrent Prolog
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   Chapter 4 VLSI for Parallel Execution of Prolog
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   Chapter 5 Supporting Functional and Logic Programming Languages through a Data Parallel VLSI Architecture
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   Chapter 6 Translating Declaratively Specified Knowledge and Usage Requirements into a Reconfigurable Machine
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   Chapter 7 VLSI-Appropriate Garbage Collection Support
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   Chapter 8 A Self-Timed Circuit for a Prolog Machine
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    Chapter 9 VLSI and Rule-Based Systems
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    Chapter 10 Unify with Active Memory
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    Chapter 11 The Pattern Addressable Memory: Hardware for Associative Processing
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    Chapter 12 A High Performance Relational Algebraic Processor for Large Knowledge Bases
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    Chapter 13 A WSI Semantic Network Architecture
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    Chapter 14 A VLSI Implementation of Multilayered Neural Networks
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    Chapter 15 A Fully Digital Integrated CMOS Hopfield Network Including the Learning Algorithm
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    Chapter 16 A Neural Network for 3-D VLSI Accelerator
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    Chapter 17 Shift Invariant Associative Memory
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    Chapter 18 VLSI Bit-Serial Neural Networks
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    Chapter 19 A New CMOS Architecture for Neural Networks
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    Chapter 20 A Limited-Interconnect, Highly Layered Synthetic Neural Architecture
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    Chapter 21 VLSI-Design of Associative Networks
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    Chapter 22 Fully-Programmable Analogue VLSI Devices for the Implementation of Neural Networks
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    Chapter 23 Are Special Chips Necessary for Neural Computing?
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    Chapter 24 A VLSI Systolic Array Dedicated to Hopfield Neural Network
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    Chapter 25 An Integrated System for Neural Network Simulations