Applied Reconfigurable Computing. Architectures, Tools, and Applications

Table of Contents

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   Book Overview
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   Chapter 1 High-Level Synthesis of Memory Systems for Decoupled Data Orchestration
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   Chapter 2 Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis
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   Chapter 3 NVMulator: A Configurable Open-Source Non-volatile Memory Emulator for FPGAs
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   Chapter 4 On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs
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   Chapter 5 Design Space Exploration of Application Specific Number Formats Targeting an FPGA Implementation of SPICE
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   Chapter 6 Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System
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   Chapter 7 ArcvaVX: OpenVX Framework for  A daptive R econfigurable C omputer V ision A rchitectures
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   Chapter 8 FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing
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    Chapter 9 Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows
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    Chapter 10 DNN Model Theft Through Trojan Side-Channel on Edge FPGA Accelerator
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    Chapter 11 Towards Secure and Efficient Multi-generation Cellular Communications: Multi-mode SNOW-3G/V ASIC and FPGA Implementations
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    Chapter 12 A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment
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    Chapter 13 On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding
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    Chapter 14 Implementation of a Perception System for Autonomous Vehicles Using a Detection-Segmentation Network in SoC FPGA
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    Chapter 15 Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC
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    Chapter 16 Scalable and Energy-Efficient NN Acceleration with GPU-ReRAM Architecture
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    Chapter 17 On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS $$^{64}$$ 64
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    Chapter 18 Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning
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    Chapter 19 More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding
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    Chapter 20 Energy Efficient DNN Compaction for Edge Deployment
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    Chapter 21 TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs
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    Chapter 22 An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits
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    Chapter 23 A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA
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    Chapter 24 Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology
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    Chapter 25 A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography
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    Chapter 26 Simulation and Modelling for Network-on-Chip Based MPSoC
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    Chapter 27 A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing