↓ Skip to main content
What is this page? Embed badge

Designing with Xilinx® FPGAs

Overview of attention for book
Cover of 'Designing with Xilinx® FPGAs'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 State-of-the-Art Programmable Logic
  3. Altmetric Badge
    Chapter 2 Vivado Design Tools
  4. Altmetric Badge
    Chapter 3 IP Flows
  5. Altmetric Badge
    Chapter 4 Gigabit Transceivers
  6. Altmetric Badge
    Chapter 5 Memory Controllers
  7. Altmetric Badge
    Chapter 6 Processor Options
  8. Altmetric Badge
    Chapter 7 Vivado IP Integrator
  9. Altmetric Badge
    Chapter 8 SysGen for DSP
  10. Altmetric Badge
    Chapter 9 Synthesis
  11. Altmetric Badge
    Chapter 10 C-Based Design
  12. Altmetric Badge
    Chapter 11 Simulation
  13. Altmetric Badge
    Chapter 12 Clocking
  14. Altmetric Badge
    Chapter 13 Stacked Silicon Interconnect (SSI)
  15. Altmetric Badge
    Chapter 14 Timing Closure
  16. Altmetric Badge
    Chapter 15 Power Analysis and Optimization
  17. Altmetric Badge
    Chapter 16 System Monitor
  18. Altmetric Badge
    Chapter 17 Hardware Debug
  19. Altmetric Badge
    Chapter 18 Emulation Using FPGAs
  20. Altmetric Badge
    Chapter 19 Partial Reconfiguration and Hierarchical Design
Attention for Chapter 19: Partial Reconfiguration and Hierarchical Design
Altmetric Badge

Citations

dimensions_citation
15 Dimensions

Readers on

mendeley
30 Mendeley
Summary Dimensions citations
So far, Dimensions has found 15 publications that cite this research output.

15

The most recent citing publications are shown below. View all 15 publications that cite this research output on Dimensions.

This page shows the most recent citations of this research output.

Click here to find out how to access more activity.

This page is provided by Altmetric.