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Chapter title |
Interconnection Modeling Challenges in System-in-Package (SiP) Design
|
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Chapter number | 59 |
Book title |
Scientific Computing in Electrical Engineering
|
Published by |
Springer, Berlin, Heidelberg, January 2006
|
DOI | 10.1007/978-3-540-32862-9_59 |
Book ISBNs |
978-3-54-032861-2, 978-3-54-032862-9
|
Authors |
S. Castorina, R. A. Ene |