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Timeline
Mendeley readers
Chapter title |
Speeding Up Verification of RTL Designs by Computing One-to-One Abstractions with Reduced Signal Widths
|
---|---|
Chapter number | 31 |
Book title |
SOC Design Methodologies
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Published by |
Springer, Boston, MA, January 2002
|
DOI | 10.1007/978-0-387-35597-9_31 |
Book ISBNs |
978-1-4757-6530-4, 978-0-387-35597-9
|
Authors |
Peer Johannsen, Rolf Drechsler, Johannsen, Peer, Drechsler, Rolf |
Mendeley readers
The data shown below were compiled from readership statistics for 1 Mendeley reader of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Unknown | 1 | 100% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Researcher | 1 | 100% |
Readers by discipline | Count | As % |
---|---|---|
Psychology | 1 | 100% |