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Automated Technology for Verification and Analysis

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Table of Contents

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    Book Overview
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    Chapter 1 Verifying VLSI Circuits
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    Chapter 2 3-Valued Abstraction for (Bounded) Model Checking
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    Chapter 3 Local Search in Model Checking
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    Chapter 4 Exploring the Scope for Partial Order Reduction
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    Chapter 5 State Space Reduction of Linear Processes Using Control Flow Reconstruction
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    Chapter 6 Automated Technology for Verification and Analysis
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    Chapter 7 TAPAAL: Editor, Simulator and Verifier of Timed-Arc Petri Nets
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    Chapter 8 CLAN: A Tool for Contract Analysis and Conflict Discovery
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    Chapter 9 UnitCheck: Unit Testing and Model Checking Combined
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    Chapter 10 LTL Model Checking of Time-Inhomogeneous Markov Chains
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    Chapter 11 Statistical Model Checking Using Perfect Simulation
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    Chapter 12 Quantitative Analysis under Fairness Constraints
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    Chapter 13 A Decompositional Proof Scheme for Automated Convergence Proofs of Stochastic Hybrid Systems
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    Chapter 14 Memory Usage Verification Using Hip/Sleek
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    Chapter 15 Solving Parity Games in Practice
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    Chapter 16 Automated Analysis of Data-Dependent Programs with Dynamic Memory
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    Chapter 17 On-the-fly Emptiness Check of Transition-Based Streett Automata
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    Chapter 18 On Minimal Odd Rankings for Büchi Complementation
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    Chapter 19 Specification Languages for Stutter-Invariant Regular Properties
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    Chapter 20 Incremental False Path Elimination for Static Software Analysis
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    Chapter 21 A Framework for Compositional Verification of Multi-valued Systems via Abstraction-Refinement
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    Chapter 22 Don’t Know for Multi-valued Systems
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    Chapter 23 Automated Technology for Verification and Analysis
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    Chapter 24 Synthesis of Fault-Tolerant Distributed Systems
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    Chapter 25 Formal Verification for High-Assurance Behavioral Synthesis
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    Chapter 26 Dynamic Observers for the Synthesis of Opaque Systems
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    Chapter 27 Symbolic CTL Model Checking of Asynchronous Systems Using Constrained Saturation
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    Chapter 28 LTL Model Checking for Recursive Programs
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    Chapter 29 On Detecting Regular Predicates in Distributed Systems
Attention for Chapter 12: Quantitative Analysis under Fairness Constraints
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Chapter title
Quantitative Analysis under Fairness Constraints
Chapter number 12
Book title
Automated Technology for Verification and Analysis
Published by
Springer, Berlin, Heidelberg, October 2009
DOI 10.1007/978-3-642-04761-9_12
Book ISBNs
978-3-64-204760-2, 978-3-64-204761-9
Authors

Christel Baier, Marcus Groesser, Frank Ciesinski, Baier, Christel, Groesser, Marcus, Ciesinski, Frank

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X Demographics

The data shown below were collected from the profile of 1 X user who shared this research output. Click here to find out more about how the information was compiled.
Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Argentina 1 50%
Unknown 1 50%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 1 50%
Unknown 1 50%
Readers by discipline Count As %
Computer Science 1 50%
Unknown 1 50%