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Timeline
Chapter title |
Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking
|
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Chapter number | 30 |
Book title |
Correct Hardware Design and Verification Methods
|
Published by |
Springer, Berlin, Heidelberg, October 2003
|
DOI | 10.1007/978-3-540-39724-3_30 |
Book ISBNs |
978-3-54-020363-6, 978-3-54-039724-3
|
Authors |
Malay K Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar |