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Correct Hardware Design and Verification Methods

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Table of Contents

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    Book Overview
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    Chapter 1 What Is beyond the RTL Horizon for Microprocessor and System Design?
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    Chapter 2 The Charm e of Abstract Entities
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    Chapter 3 The PSL/Sugar Specification Language A Language for all Seasons
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    Chapter 4 Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular
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    Chapter 5 Predicate Abstraction with Minimum Predicates
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    Chapter 6 Efficient Symbolic Model Checking of Software Using Partial Disjunctive Partitioning
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    Chapter 7 Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP
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    Chapter 8 A Hazards-Based Correctness Statement for Pipelined Circuits
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    Chapter 9 Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
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    Chapter 10 On Complementing Nondeterministic Büchi Automata
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    Chapter 11 Coverage Metrics for Formal Verification
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    Chapter 12 “More Deterministic” vs. “Smaller” Büchi Automata for Efficient LTL Model Checking
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    Chapter 13 An Optimized Symbolic Bounded Model Checking Engine
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    Chapter 14 Constrained Symbolic Simulation with Mathematica and ACL2
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    Chapter 15 Semi-formal Verification of Memory Systems by Symbolic Simulation
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    Chapter 16 CTL May Be Ambiguous When Model Checking Moore Machines
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    Chapter 17 Reasoning about GSTE Assertion Graphs
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    Chapter 18 Towards Diagrammability and Efficiency in Event Sequence Languages
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    Chapter 19 Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving
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    Chapter 20 On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking
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    Chapter 21 On the Correctness of an Intrusion-Tolerant Group Communication Protocol
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    Chapter 22 Exact and Efficient Verification of Parameterized Cache Coherence Protocols
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    Chapter 23 Design and Implementation of an Abstract Interpreter for VHDL
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    Chapter 24 A Programming Language Based Analysis of Operand Forwarding
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    Chapter 25 Integrating RAM and Disk Based Verification within the Mur ϕ Verifier
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    Chapter 26 Design and Verification of CoreConnect TM IP Using Esterel
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    Chapter 27 Inductive Assertions and Operational Semantics
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    Chapter 28 A Compositional Theory of Refinement for Branching Time
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    Chapter 29 Linear and Nonlinear Arithmetic in ACL2
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    Chapter 30 Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking
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    Chapter 31 Convergence Testing in Term-Level Bounded Model Checking
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    Chapter 32 The ROBDD Size of Simple CNF Formulas
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    Chapter 33 Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems
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    Chapter 34 Finite Horizon Analysis of Markov Chains with the Mur ϕ Verifier
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    Chapter 35 Improved Symbolic Verification Using Partitioning Techniques
Attention for Chapter 11: Coverage Metrics for Formal Verification
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Chapter title
Coverage Metrics for Formal Verification
Chapter number 11
Book title
Correct Hardware Design and Verification Methods
Published by
Springer, Berlin, Heidelberg, October 2003
DOI 10.1007/978-3-540-39724-3_11
Book ISBNs
978-3-54-020363-6, 978-3-54-039724-3
Authors

Hana Chockler, Orna Kupferman, Moshe Y. Vardi

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Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 3 100%

Demographic breakdown

Readers by professional status Count As %
Student > Doctoral Student 1 33%
Student > Master 1 33%
Unknown 1 33%
Readers by discipline Count As %
Computer Science 2 67%
Unknown 1 33%