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Timeline
Chapter title |
Device Optimization to Assess Losses and Ringing Issues in Integrated Synchronous Buck Converters
|
---|---|
Chapter number | 17 |
Book title |
Analog Circuit Design
|
Published by |
Springer, Dordrecht, January 2012
|
DOI | 10.1007/978-94-007-1926-2_17 |
Book ISBNs |
978-9-40-071925-5, 978-9-40-071926-2
|
Authors |
J. Roig, F. Bauwens |