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Power-constrained Testing of VLSI Circuits

Overview of attention for book
Power-constrained Testing of VLSI Circuits
Springer US

Table of Contents

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    Book Overview
  2. Altmetric Badge
    Chapter 1 Design and Test of Digital Integrated Circuits
  3. Altmetric Badge
    Chapter 2 Power Dissipation During Test
  4. Altmetric Badge
    Chapter 3 Approaches to Handle Test Power
  5. Altmetric Badge
    Chapter 4 Power Minimization Based on Best Primary Input Change Time
  6. Altmetric Badge
    Chapter 5 Test Power Minimization Using Multiple Scan Chains
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    Chapter 6 Power-conscious Test Synthesis and Scheduling
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    Chapter 7 Power Profile Manipulation
  9. Altmetric Badge
    Chapter 8 Conclusion
Attention for Chapter 2: Power Dissipation During Test
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Summary
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Chapter title
Power Dissipation During Test
Chapter number 2
Book title
Power-constrained Testing of VLSI Circuits
Published by
Springer, Boston, MA, January 2004
DOI 10.1007/0-306-48731-4_2
Book ISBNs
978-1-4020-7235-2, 978-0-306-48731-6
View on publisher site
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