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Timeline
Chapter title |
Technology Mapping
|
---|---|
Chapter number | 5 |
Book title |
Logic Synthesis and Verification
|
Published by |
Springer, Boston, MA, January 2002
|
DOI | 10.1007/978-1-4615-0817-5_5 |
Book ISBNs |
978-1-4613-5253-2, 978-1-4615-0817-5
|
Authors |
Leon Stok, Vivek Tiwari, Stok, Leon, Tiwari, Vivek |