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Mendeley readers
| Chapter title |
Automatic hardware synthesis of nested loops using UET grids and VHDL
|
|---|---|
| Chapter number | 87 |
| Book title |
High-Performance Computing and Networking
|
| Published by |
Springer, Berlin, Heidelberg, April 1997
|
| DOI | 10.1007/bfb0031660 |
| Book ISBNs |
978-3-54-062898-9, 978-3-54-069041-2
|
| Authors |
Nectarios Koziris, Theodore Andronikos, George Economakos, George Papakonstantinou, Panayotis Tsanakas, Koziris, Nectarios, Andronikos, Theodore, Economakos, George, Papakonstantinou, George, Tsanakas, Panayotis |
Mendeley readers
The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
| Country | Count | As % |
|---|---|---|
| Unknown | 3 | 100% |
Demographic breakdown
| Readers by professional status | Count | As % |
|---|---|---|
| Professor | 1 | 33% |
| Librarian | 1 | 33% |
| Student > Ph. D. Student | 1 | 33% |
| Readers by discipline | Count | As % |
|---|---|---|
| Computer Science | 2 | 67% |
| Unknown | 1 | 33% |