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Mendeley readers
Chapter title |
Verification of synchronous circuits by symbolic logic simulation
|
---|---|
Chapter number | 21 |
Book title |
Hardware Specification, Verification and Synthesis: Mathematical Aspects
|
Published in |
Lecture notes in computer science, May 2005
|
DOI | 10.1007/0-387-97226-9_21 |
Book ISBNs |
978-0-387-97226-8, 978-0-387-34801-8
|
Authors |
Randal E. Bryant |
Mendeley readers
The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Unknown | 3 | 100% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Professor | 3 | 100% |
Readers by discipline | Count | As % |
---|---|---|
Computer Science | 2 | 67% |
Engineering | 1 | 33% |