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Chapter title |
Design and Verification of 16-Bit Vedic Multiplier Using 3:2 Compressors and 4-Bit Novel Adder
|
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Chapter number | 83 |
Book title |
Proceeding of International Conference on Intelligent Communication, Control and Devices
|
Published by |
Springer Singapore, January 2017
|
DOI | 10.1007/978-981-10-1708-7_83 |
Book ISBNs |
978-9-81-101707-0, 978-9-81-101708-7
|
Authors |
K. Venkata Siva Reddy, P. Vishnu Kumar, K. Maheswari, B. Khaleelu Rehman |
Editors |
Rajesh Singh, Sushabhan Choudhury |